An essential element of design in digital systems that broadly affects system performance is the creation and distribution of a precise clock signal to serve as a stable timing reference for synchronizing digital logic, particularly for sampling analog signals prior to their conversion to a digital form or for converting digital signals back to an analog form. As the role of digital logic becomes more pervasive in numerous signal-processing applications, and as the conversion of signals to digital format occurs earlier in the signal processing chain to reduce system cost and size, system performance in numerous applications such as cellular telephony and high-performance television receivers is limited by clock signal timing jitter. Applications requiring signal sampling are also frequently found in switched-capacitor system implementations and in fiber-optic systems. Clock signal timing jitter is now generally recognized as a fundamentally limiting factor of the accuracy of a signal processing sequence.
The noise contribution due to the uncertainty of the sampling instant of a high frequency input signal is directly affected by timing jitter in both the clock source and the clock distribution network. The external sinusoidal time reference produced by a low phase-noise source is usually bandpass filtered to reduce short-term timing uncertainty, usually using an external quartz filter which can reduce timing jitter from 1 ps to less than 100 fs, and is converted into a differential sinusoidal waveform using a transformer. Differential waveforms are generally the cleanest and most power-efficient signal arrangements for high-frequency synchronization. The use of external narrow-band filters to reduce short-term timing uncertainty of a sinusoidal signal is described by A. Zanchi, et al., in the paper titled “Measurement and Spice Prediction of Sub-Picosecond Clock Jitter in A-to-D Converters,” in the Proceedings of the ISCAS 2003, held in Bangkok, Thailand, May, 2003, on pages 557-560. But before a two-phase, non-overlapped, clock generation circuit that supplies downstream logic elements can be driven, the clock signal must be preconditioned, which is usually accomplished using a low-noise clock-signal preamplifier.
The general function of a front-end clock signal preamplifier is to amplify and convert a sinusoidal timing reference signal into a clock signal with a rectangular waveform supplied on a differential output that is precisely time aligned with the original sinusoidal reference signal, and without timing jitter in the amplification and conversion process. A clock signal with a rectangular waveform is generally used to gate the periodic sampling instant for analog-to-digital converters (ADCs). Differential outputs are generally used to reduce the common-mode component of a signal; however, the differential output of the preamplifier can be used in both a differential clock distribution circuit, or a single-ended one.
The performance of ADCs can be directly related to timing jitter by a well-known formula described by M. Shinagawa, et al., in “Jitter Analysis of High Frequency Sampling Systems,” published in the IEEE Journal of Solid State Circuits, Vol. 25, No. 1, February 1990, on pages 220-224:SNRjitter=−20·log10(2πƒINσT),where SNRjitter is the signal-to-noise contribution (in dB) to the digital signal due to sampling timing jitter of the incoming analog signal, fIN is the nominal frequency (in Hz) of the signal being sampled, and σT is the rms (root-mean square) timing jitter (in seconds) of the periodic sampling process. Intuitively, the noise produced by an ADC is proportional to the timing jitter and the slope of the voltage waveform being converted. The noise contribution due to quantization, i.e., due to imprecisely representing a signal with a limited number of bits, can be estimated from the equation:SNRquantization=1.5+6·k,where SNRquantization is the noise contribution in dB due to quantizing the data, and k is the number of bits used to represent the data, as described by R. A. Haddad, et al., in “Digital Signal Processing,” W. H. Freeman and Co., 1991, page 38. The equation above has been adjusted to reflect typical ADC rms input voltage relative to the full-scale input voltage of the ADC. Thus, when performing digital conversion, for example, for a 65 MS/s (megasamples per second) signal using a 16 bit ADC with 300 ps of timing jitter, the theoretical signal-to-noise ratio (SNR) is dominated by almost 20 dB by the effect of the timing jitter in the sampling process over the effect of the 16-bit quantization.
A typical two-phase clock generation and distribution circuit of the prior art is shown in FIG. 1. A differential input voltage signal with a sinusoidal waveform is coupled to the clock signal preamplifier 102 at circuit node 101. The clock signal preamplifier provides clock signal amplification, conversion to a rectangular waveform sufficient in output level for coupling to the downstream circuit blocks. A two-phase clock-signal generator, 104, typically formed with inverters such as inverter 106, and NAND gates, such as NAND gate 108, with rectangular-waveform outputs, produces two-phase clock output signals such as on leads 103 and 105. The rectangular waveform clock signals are distributed to downstream logic circuits as needed, such as by distribution buffer 112, typically formed with additional inverters, such as inverter 114 and inverter 110.
The timing jitter of the clock phase driving a signal sampling device, which ultimately limits the signal-to-noise figure of an ADC or any sampled-signal arrangement, is the rms sum of the jitter contributions from the cascaded signal-processing blocks, i.e., from the external signal source, through the clock signal preamplifier, and through the chain of buffers such as illustrated in FIG. 1. Each element of the clock signal processing chain contributes edge jitter to the clock signal.
The general problem of minimization of the overall timing jitter, can be described as follows:
a) To reduce the clock source noise, narrow-band filtering of the external signal source is required. In the frequency range of tens of MHz, the best instrumentation available to date, such as an HP8644B low phase-noise signal source or a Wenzel signal generator, synthesizes sinusoids with jitter in excess of 1.3 ps; after a narrow bandpass crystal filter, the phase noise contribution can be reduced to about 25 fs, as described by A. Zanchi, et al., “Measurement and Spice Prediction of Sub-Picosecond Clock Jitter in A-to-D Converters,” as cited above. Thus, a differential low-noise sinusoidal clock source is now the preferred choice to sample high-speed, high-amplitude input signals.
b) The timing jitter contribution of a single signal inverter is related to the size of its components. The bigger a MOSFET gate, the smaller the jitter due to thermal noise, as described by A. Zanchi, et al., in “A 16-Bit 65 MS/s 3.3 V Pipeline ADC Core in SiGe BiCMOS with 78-dB SNR and 180 fs Jitter,” in press for the IEEE Journal of Solid-State Circuits, June 2005, and to the efficacy of decoupling against supply bounce. However, for the technology at hand, an upper bound for the digital inverter timing jitter contribution can be determined by simulation to be about 70 fs.
c) Since the prior art preamplifiers introduce timing jitter ranging from 500 fs down to 180 fs, as described by A. Zanchi, et al., in “A 16-Bit 65 MS/s 3.3 V Pipeline ADC Core in SiGe BiCMOS with 78-dB SNR and 180 fs Jitter”, cited above, and given the quadratic nature of jitter addition from multiple (statistically independent) noise sources, i.e., that the variances of independent noise sources add, it is apparent that the preamplifier is the greatest contributor to the timing jitter limitation for the signal-to-noise ratio inside a chip.
Several prior art preamplifier circuits have been presented such as by A. R. Bugeja, et al., in “Design of a 14 b 100 MS/s switched-capacitor Pipelined ADC in RFSiGe BiCMOS,” in the Proceedings of the ISCAS 2001, held in Sydney Australia, in May 2001, on pages 428-431, in the datasheet for the LTC 1748 14-bit, 80 MS/s Low Noise ADC, Linear Technology Corp., 2003, page 15, and by A. Zanchi, et al., “A 16-Bit 65 MS/s 3.3 V Pipeline ADC Core in SiGe BiCMOS with 78-dB SNR and 180 fs Jitter,” as cited above, and are illustrated in FIGS. 2A, 2B, and 2C, respectively.
Turning to FIG. 2A, illustrated is a clock signal preamplifier circuit of the prior art with resistive passive loads formed with differentially coupled n-channel MOSFETs 206 and 208 that are coupled to a differential sinusoidal input signal. The input signal is coupled to circuit nodes VINP and VINN. The circuit is powered from a bias voltage source coupled to the circuit nodes VDD and VSS. N-channel MOSFET 210, in series with MOSFETs 206 and 208, is operated as a current source at a current level of about 6 mA by application of a controlled voltage to its gate terminal on lead 212. The drains of MOSFETs 206 and 208 are coupled to the passive pull-up resistors R1 and R4, and to the drains of p-channel MOSFETs 202 and 204. The gates of MOSFETs 202 and 204 are coupled to the common circuit node of resistors R1 and R4, so that MOSFETs 202 and 204 define the dc level for the outputs of the preamplifier and synthesize, from an ac perspective, a low-impedance differential diode-connected load tied to the VDD circuit node in which 6 mA of current also flow in total. The output voltage from the clock-signal preamplifier, which is a rectangular waveform signal, can either be supplied differentially on circuit nodes VINTP and VINTN, i.e., the output voltage is one circuit node voltage minus the other, or as in the present embodiment, can be supplied as a single-ended signal to separate inverters (as illustrated in FIG. 1). In the differential case, the voltage gain of the circuit is the transconductance of one input MOSFET, i.e., MOSFET 206 or 208, times the resistance of R1 or R4, which are assumed to be equal. The transition speed of the output voltage of this circuit at the transition times of the rectangular waveform, which is related to its output timing jitter, is limited by the passive pull-up arrangement of the resistors R1 and R4 and parasitic circuit capacitance, and these circuit elements contribute to limiting the ultimate timing performance of the circuit due to the limited slope of the voltage transitions. The same principle applies to resistance-loaded preamplifier topologies which do not make use of P-type devices used as diodes in parallel with the resistors.
An improved version of the clock-signal preamplifier circuit illustrated in FIG. 2A is the prior-art clock signal preamplifier circuit using PMOS active loads illustrated in FIG. 2B. Again, this circuit is formed with a pair of differentially connected n-channel MOSFETs, 226 and 228, that are coupled to the input signals, VINP and VINN. The circuit is powered from a bias voltage source coupled to the circuit nodes VDD and VSS. A 6 mA current source is provided by the n-channel MOSFET 230, controlled by a voltage applied to its gate terminal on lead 232. The loads for the differentially connected MOSFETs 226 and 228 are formed with p-channel MOSFETs 222 and 224, controlled by a voltage applied to their gate leads, 234. The MOSFETs 222 and 224 provide a much higher impedance for the drains of MOSFETs 226 and 228 than the resistors R1 and R4 shown in FIG. 2A. Nonetheless, the differential output voltage on circuit nodes VINTP and VINTN is still driven by passive loads such as formed with MOSFETs 222 and 224 and loaded with inherent circuit parasitic capacitance. The voltage gain of the circuit is the transconductance of one input MOSFET, i.e., MOSFET 226 or 228, times the parallel drain resistance of MOSFETs 224 and 228 or MOSFETs 222 and 226. Thus, the output impedance of the circuit is higher than the circuit illustrated in FIG. 2A. The transition speed of the output voltage of this circuit and its timing jitter are again limited by the passive pull-up arrangement of the MOSFETs 222 and 224 and the circuit parasitic capacitance. Although the gain of this circuit is higher than the gain of the circuit illustrated in FIG. 2A, its noise is also higher, resulting in little or no improvement in its timing jitter.
A third version from the prior art of a clock-signal preamplifier circuit using a PMOS pseudo-latch which provides positive feedback during the voltage transition of the output clock signal is illustrated in FIG. 2C. The circuit is formed with a pair of differentially connected n-channel MOSFETs 246 and 248 that are coupled to the input signals on circuit nodes VINP and VINN. A 6 mA current source is provided by the n-channel MOSFET 250, controlled by a voltage applied to its gate terminal on lead 252. The circuit is powered from a bias voltage source coupled to the circuit nodes VDD and VSS. In this circuit, the slope of the pull-up edge of the single-ended output voltages at nodes VINTP and VINTN is increased by the inclusion of cross-coupled MOSFETs 242 and 244, which improves the total jitter of the clock-signal rectangular waveform output signal by about 50%. Nonetheless, MOSFETs 242 and 244 provide limited switching speed at the pull-down transitions of the rectangular waveform outputs, which still limits the timing jitter that can be produced by such a circuit. In particular, at lower sampling frequencies the inherent hysteresis built into the circuit adversely impacts the jitter performance of this solution, making it worse than the aforementioned prior art for rates of 30MS/s or lower in the present technology.
The main limitations of the prior art circuits are thus passive pull-up of the output, which results in slow transition times, making them more sensitive to timing uncertainties, and forced usage of MOSFET devices to yield larger output swings, which generally results in reduced output voltage transition slopes and higher device noise (e.g., a 1/f-dependent noise component), in turn requiring additional buffer stages which introduce more sources of jitter, as described by A. Zanchi, et al., in “A 16-Bit 65 MS/s 3.3 V Pipeline ADC Core in SiGe BiCMOS with 78-dB SNR and 180 fs Jitter”, cited above, and by J. A. McNeill, “Jitter in Ring Oscillators,” published in the IEEE Journal of Solid-State Circuits, Vol. 32, No. 6, June 1997, on pages 870-879.
Thus, the prior art approach uses passive pull-up circuits and/or cross-coupled transistors in the clock-signal preamplifier to produce a rectangular clock output waveform. Despite the advances in clock-signal preamplifiers, a remaining obstacle to obtaining low timing jitter in the conversion of a sinusoidal timing reference signal to an amplified and rectangular waveform signal is the need to increase the slope of the output voltage waveform at its voltage transition points so that the preamplifier introduces less timing signal jitter in the generation of a rectangular output waveform.
A need thus exists for a clock-signal preamplifier that can amplify a sinusoidal timing reference signal, convert it to a rectangular waveform, and produce output voltage transitions with increased slope, resulting in less timing jitter of the output voltage waveform than is achieved by the prior art.